1. Field of the Invention
This invention relates to semiconductor structures, and in particular to oxide-isolated integrated circuit structures having specially shaped buried layers.
2. Description of the Prior Art
Oxide-isolated semiconductor structures and integrated circuits are well known in the art. See, e.g., U.S. Pat. No. 3,648,125 entitled "METHOD OF FABRICATING INTEGRATED CIRCUITS WITH OXIDIZED ISOLATION AND THE RESULTING STRUCTURE" issued to Douglas L. Peltzer. Also well known are techniques for forming buried layers in oxide-isolated integrated circuits. For example, FIGS. 10a, 10b and 10c of the above-cited patent depict a typical prior-art processing sequence for fabricating a buried layer 43a in a semiconductor substrate 41, and then forming oxidized isolation regions.
A typical process for manufacturing such a prior art oxide-isolated integrated circuit structure includes diffusing n-type impurity into the p-type silicon substrate to form the buried layer using a silicon dioxide layer as a diffusion mask . The silicon dioxide is then removed and an epitaxial layer of silicon grown on the surface of the substrate. The upper surface of the epitaxial layer and the upper surface of the buried layer are each essentially flat, although displaced from one another by approximately the thickness of the epitaxial layer. A silicon nitride layer is then formed and partially removed to provide a mask for etching the epitaxial layer where regions of oxide isolation are desired. The epitaxial layer is etched and then oxidized down to the buried layer to electrically isolate pockets in the epitaxial layer. Active and/or passive electronic components may be formed in these pockets.
Unfortunately, prior-art structures such as the one described suffer from several disadvantages. First, the epitaxial layer must be etched to such a deep depth to obtain effective oxide isolation that the upper surface to the integrated circuit structure becomes significantly non-planar. It is well known in the semiconductor manufacturing arts that non-planar surfaces present numerous processing difficulties; for example, it is difficult to traverse such non-planar surfaces with thin reliable metal connections. Another disadvantage of such prior-art structures is that the mask for etching the epitaxial layer to form the regions of oxide isolation must be carefully aligned with respect to the buried layer to obtain acceptable electrical isolation.
Accordingly, it is an object of this invention to create a more uniformly planar integrated circuit structure, to improve the electrical isolation characteristics of oxidized insulation, and to increase the alignment tolerances between the mask for diffusing the buried layer and the mask for etching the silicon for the oxidized isolation regions.